1. Technical Field
The present invention relates generally to programmable logic devices, and more particularly to field programmable gate arrays (FPGAs) having a non-non-programming-based default power-on electronic configuration to shorten the power-up, reconfiguration and/or reset time.
2. Related Art
Programmable logic devices (PLDs) are a well-known type of integrated circuit (IC) that may be programmed by a circuit designer to perform user-specified logic functions. One common type of PLD is a field programmable gate array (FPGA). An FPGA is a general purpose programmable device that is customizable by an end user to realize a desired user-specific circuit. Typically, the FPGA includes fabric elements such as configurable logic blocks (CLBs), input/output blocks (IOBs), and an interconnect that programmably connects the CLBs and IOBs. The function or configuration of the CLBs, IOBs, and interconnect is determined by an externally stored bitstream. The bitstream is a stream of control bits and is generally stored in an external device including non-volatile memory, such as read only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), floppy disk, hard disk file, or network. Either at a power-up “configuration” phase or a “reconfiguration” phase after power-up, the stored bitstream and/or control bits are loaded in the fabric elements of the FPGA. That is, configuration/reconfiguration can be viewed as a process of loading/reloading the bitstream and/or control bits into the configuration memory cells which control the programmable interconnect structure, the IOBs, and the CLBs. Therefore, the bitstream and/or control bits can usually be termed “configuration data.”
The configuration data is loaded into and held in memory cells in the FPGA via an interface circuit. The interface circuit may include a standard serial interface available on present FPGA devices. The memory cells (or configuration memory cells) of the FPGA itself may be implemented using volatile or non-volatile memory technology, such as static random access memory (SRAM) technology, thereby facilitating reconfiguration and providing design flexibility. The SRAM memory cell controls one or more transistors at the configurable points in the FPGA or serves as one or more entries in a lookup table. The configuration memory cells collectively determine what functions the FPGA will implement.
Some commercially available SRAM FPGAs, for example, the FPGA products from Altera Corporation or Xilinx, Inc., have a stream-based interface to the SRAM configuration memory. For some stream based interfaces, in order to make any changes in the configuration, an entire section of the configuration memory must be reloaded. Configuration information may be loaded from a variety of sources, for example, from the memory accessed by a microprocessor, from a non-volatile PROM under control of the FPGA itself (see U.S. Reissue Pat. No. 34,363), or by mapping the FPGA configuration memory into the address space of the microprocessor. Should it become desirable to change or update the configuration of the FPGA, e.g., so as to enable the FPGA to be used with other devices of varying configurations and compatibility standards, the associated external memory is re-programmed with the new configuration design. Upon subsequent boot-up, the FPGA then reads the new configuration design from the associated external memory, and then configures itself accordingly.
In this design and arrangement, FPGAs provide extreme flexibility in implementing an electrical circuit because the logical functions and interconnection of logic elements can be configured without additional fabrication process steps. Accordingly, because of the ease in changing the logical configuration of the logic elements, FPGAs are recognized as a time and resource efficient method for verifying the design of the electrical circuit.
However, there are some drawbacks in the current standard FPGA operation, especially during a power-up or reconfiguration phase. The configuration of the FPGA, which is determined by the externally stored bitstream and/or control bits, is typically loaded from a non-volatile configuration memory into the SRAM configuration memory cells when power is applied to the FPGA device. Upon power-up or during a reconfiguration time after power-up, the FPGA under the current design first goes into a “disabled” mode for a transient time period. In the “disabled” mode, the functional state of the FPGA is not yet established, i.e., non-functional state, and it is not yet useful. The externally stored bitstream has to be loaded into the FPGA to facilitate later functional operations. However, the transient time period for the external bitstream loading normally consumes up to several seconds. This is relatively a long time in terms of an integrated circuit, which generally measures each instruction time/cycle in ns (10^−9S) or even ps (10^−12S). Therefore, a need exists in the FPGA art for a system and method to shorten such a long transient time to speed up the FPGA operation, especially during the FPGA power-up or reconfiguration phase.